/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-18 10:53:49
 *
 */


#ifndef ANLG_PHY_G1_H
#define ANLG_PHY_G1_H

#define CTL_BASE_ANLG_PHY_G1 0x323B4000


#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_ANA_MPHY_CTRL2      ( CTL_BASE_ANLG_PHY_G1 + 0x0000 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TEST_REG       ( CTL_BASE_ANLG_PHY_G1 + 0x0004 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_EFUSE_REG      ( CTL_BASE_ANLG_PHY_G1 + 0x0008 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_POWER_REG      ( CTL_BASE_ANLG_PHY_G1 + 0x000C )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RESERVED_REG   ( CTL_BASE_ANLG_PHY_G1 + 0x0010 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_APB_REG        ( CTL_BASE_ANLG_PHY_G1 + 0x0014 )
#define REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_REG_SEL_CFG_0       ( CTL_BASE_ANLG_PHY_G1 + 0x0018 )

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_ANA_MPHY_CTRL2 */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_CFGCLK_FREQ(x)         (((x) & 0xFF) << 9)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_REFCLKON                  BIT(8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_MAIN_RESET_0           BIT(7)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_RESET_0                BIT(6)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_LINERESET_0            BIT(5)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_MAIN_RESET_0           BIT(4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_RESET_0                BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_LINERESET_0            BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_RESET                  BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_ATTRRESET              BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TEST_REG */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_DIFNDRIVE_0            BIT(25)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_CONTROLLED_ACTTIMER_0  BIT(24)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_TST_RTCONTROL_0(x)     (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_TST_RTCONTROL_0(x)     (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TST_RTCONTROL(x)       (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_EFUSE_REG */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TRIMBG(x)              (((x) & 0xF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TRIMTXTERM(x)          (((x) & 0xF) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TRIMRXTERM(x)          (((x) & 0xF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_POWER_REG */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_PS_PD_L                   BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_PS_PD_S                   BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_ISO_SW_EN                 BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_ANA_POWERDOWN             BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RESERVED_REG */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RESERVEDI(x)              (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RESERVEDO(x)              (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_APB_REG */

#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_TST_RTOBSERVE_0(x)     (((x) & 0xFF) << 20)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_TST_RTOBSERVE_0(x)     (((x) & 0xFF) << 12)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TST_RTOBSERVE(x)       (((x) & 0xFF) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_APB_PRESETN               BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_BISTON                    BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_BISTDONE                  BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_MPHY_BISTOK                    BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_MIPI_MPHY_1T1R_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_CFGCLK_FREQ    BIT(17)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_REFCLKON          BIT(16)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_MAIN_RESET_0   BIT(15)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_RESET_0        BIT(14)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_TX_LINERESET_0    BIT(13)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_MAIN_RESET_0   BIT(12)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_RX_RESET_0        BIT(11)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_RESET          BIT(10)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_ATTRRESET      BIT(9)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TRIMBG         BIT(8)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TRIMTXTERM     BIT(7)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_CB_TRIMRXTERM     BIT(6)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_PS_PD_L           BIT(5)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_PS_PD_S           BIT(4)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_ISO_SW_EN         BIT(3)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_ANA_POWERDOWN     BIT(2)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_RESERVEDI         BIT(1)
#define BIT_ANLG_PHY_G1_DBG_SEL_ANALOG_MIPI_MPHY_1T1R_MPHY_BISTON            BIT(0)


#endif /* ANLG_PHY_G1_H */


